FIG. 7 shows a prior art refractory metal self aligned gate FET. In FIG. 7, reference numeral 1 designates a semi-insulating GaAs substrate. An active layer 2 is disposed in a (100) GaAs substrate 1. A gate electrode 3 comprising tungsten silicide is disposed on the active layer 2. High dopant concentration layers 4a and 4b are disposed in the GaAs substrate 1. Ohmic electrodes 5a and 5b are disposed on the layers 4a and 4b, respectively. The reference character IF.sub.3 designates compressive stress from the insulating film 6 applied to the end of gate electrode 3 and reference character IF.sub.4 designates tensile stress in the tungsten silicide at the end of the gate electrode 3.
In this prior art example, a tensile stress F.sub.4 caused by the tungsten silicide 3 and a compressive stress F.sub.3 caused by the insulating film 6 are applied to the gate electrode 3. When such stresses are generated at the end of gate electrode 3, the semi-insulating GaAs substrate 1 is distorted below the gate electrode 3, and piezoelectric charges are generated in the substrate directly below the gate electrode 3. A distribution of positive and negative charges is generated as is generally known.
FIG. 10 shows the distribution of piezoelectric charges shown in IEEE Transactions on Electron Devices, Vol. ED-31, No. 10. 1984. In FIG. 10, reference numeral 10 designates a semi-insulating GaAs substrate, reference numeral 13 designates a gate electrode, reference numerals 16a and 16b designate insulating films (Si.sub.3 N.sub.4), and reference character F designates a stress applied to the end of gate electrode 13 from the insulating films 16a and 16b. When the stress F is generated, distortion occurs in the substrate 10. Herein, when a compound semiconductor such as a semi-insulating GaAs substrate is used for the substrate, Ga and As atoms produce a polarization due to the distortion and the distribution of piezoelectric charges vary dependent on the crystalline direction in the substrate. For example, when stresses as shown in FIG. 7 are generated at the end of gate electrode 3, the positive charges increase in the [011] direction of GaAs with a (100) crystal face, while negative charges increase in the [011] direction thereof, and the piezoelectric charges are not generated in the [010] direction.
It is generally known that as the gate length is shortened, the short channel effect arises in which the threshold voltage is shifted toward the negative side. When the distribution of piezoelectric charges arising due to the stress applied to the substrate varies with the crystalline direction of the substrate, as in compound semiconductors such as GaAs as discussed above, the short channel effect vanes dependent on the direction of the gate electrode 3 of the field effect transistor which is produced on the substrate. FIG. 8 shows the gate direction dependence of the short channel effect where the field effect transistor has the stresses as shown in FIG. 7. As shown in the figure, the controllability and the variation of the V.sub.th are stable in an FET having a [010] gate direction, while the V.sub.th shift due to the short channel effect is large in the FET having a [011] gate direction. Furthermore, the .differential.V.sub.th /.differential.L.sub.g at the submicron region is unfavorably large in an FET having a [610] gate direction.
FIGS. 9(a) and 9(b) show a circuit diagram and a plan view of a pattern arrangement in a case where an integrated circuit is constructed using the field effect transistors shown in FIG. 7. FIG. 9(a) shows a circuit construction for DCFL (Direct Coupled FET Logic) and FIG. 9b) shows a pattern diagram thereof.
In FIG. 9(b), reference numerals 7a and 7b designate gate electrode pads, reference numerals 8a, 8b, 8c designate ohmic contact electrodes, and reference numeral 9 designates ground. As shown in FIG. 9b), the ohmic electrodes 8a and 8b function as a source electrode and a drain electrode associated with the gate electrode 7a, and the ohmic electrodes 8b and 8c function as a source electrode and a drain electrode associated with the gate electrode 7b, and the ohmic electrode 8b and gate electrode 7b, and the ohmic electrode wiring 8a and ground 9 are connected by wire bondings 11b and 11a, respectively. When an integrated circuit is constructed including the field effect transistors of FIG. 7, the direction of gate electrode 3 which is disposed on the semi-insulating GaAs substrate 1 should be the same direction in all cases. As shown in FIG. 9b ) from the crystal direction dependence of the piezoelectric charges distribution generated directly below the gate electrode 3 of the field effect transistor, the gate electrode wiring 7b should be patterned in the same direction as the gate electrode wiring 7a, thereby resulting in a rectangular pattern configuration.
The prior art semiconductor device of such a construction has following problems because of the crystal direction dependence of piezoelectric charges generated below the gate electrode 3.
1) When an FET having [011] gate direction is adopted, the V.sub.th shift due to the short channel effect is large and the controllability of V.sub.th is low.
2) When an FET of [011] gate direction is adopted, the .differential.V.sub.th /.differential.L.sub.g for a submicron gate length is increased and the V.sub.th is likely to be affected by variations in gate length, increasing the variation of V.sub.th.
3) When an FET having [010] direction is adopted, the controllability and variation of V th are improved but there is crystal breakage in this direction, thereby requiring another device in producing a mask. Further, the chip size is unfavorably increased, thereby resulting in lowering of the yield.
In this way, because the threshold voltage varies with the gate direction, FETs constituting an integrated circuit are required to have the same gate direction and the degree of freedom in design is reduced, limiting the reduction of chip area.